In the case of a conventional synchronous random access memory (SRAM), a register control type is frequently used which captures a signal such as an address incoming from an external unit outside of the chip at the leading edge of a clock. For example, the official gazette of Japanese Patent Laid-Open No. 20479/1994 discloses controlling input/output of a signal at the leading edge of a clock. A conventional example of capturing an address signal by the register control type is described below in conjunction with FIGS. 14(a) and 14(b). In FIGS. 14(a) and 14(b), an address signal ADD incoming from an external unit outside of the chip is input with a setup time (ts) and a hold time (th) for the leading edge of a clock signal CLK. Therefore, the decision period of the address signal incoming from an external unit outside of the chip is shown by the following expression. EQU Signal decision period=Setup time (ts)+Hold time (th) (1)
The address signal ADD is delayed by a circuit or wiring and is input to an address register 23 through an address buffer 21, or the like. The address register 23 is controlled by a control clock CLK' so as to securely capture a desired address signal "A0" at the middle of the decision period of an address signal a1 input to the address register 23. An output of the address register 23 serving as an internal address signal ADD' is output at the timing of t0 delayed by a delay time from the leading edge of the control clock CLK' by the address register 23.
A conventional register control system captures an address signal at the leading edge of a clock. To securely capture a desired address signal, the timing of a control clock is set so as to capture the address signal at the middle of an address-signal decision period. Therefore, the address signal is captured by an address register by being delayed from the timing in which the address signal is decided. This delay corresponds to a time approx. 1/2 the address signal decision period. Thus, because an address signal captured into a chip is determined in accordance with an address register control clock, the address signal is delayed by a time approximately equal to half the address signal decision period from the timing in which an address is decided.
In order to shorten the access time and cycle time of an SRAM, it is necessary to capture an address signal into a chip simultaneously with the timing in which the address signal is decided. However, a register for capturing a signal at the leading edge of a clock cannot securely capture desired data because there is no setup margin for capturing the signal.
A latch control type using a level latch is used as a means for determining the capture of an address signal into a chip in accordance with the timing in which the address signal is decided. For example, the official gazette of Japanese Patent Laid-Open No. 67670/1994 discloses an art for latching period signals linked by a clock in the period of "Hi".